Virtex: Foundation 3.1 Error

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Dear all <BR>
&nbsp;I am using Xilinx Foundation 3.1i to implement my <BR>
design into XSV board and debug using hardware <BR>
&nbsp;debugger. <BR>
&nbsp;I am trying to instantiate readback symbol in my <BR>
design using this file : <p> library IEEE; <BR>
&nbsp;use IEEE.std_logic_1164.all; <BR>
&nbsp;library virtex; <BR>
&nbsp;use virtex.components.all; <p> entity rdbk is <BR>
&nbsp;port ( <BR>
&nbsp;rt, clk : in STD_LOGIC; <BR>
&nbsp;rd, rip_p : out STD_LOGIC <BR>
&nbsp;); <BR>
&nbsp;end rdbk; <p> architecture xilinx of rdbk is <p> begin <p> U0: RDBK port
map (TRIG =&gt; rt, DATA =&gt; rd, RIP =&gt; <BR>
&nbsp;rip_p); <BR>
&nbsp;U1: RDCLK port map (I =&gt; clk); <p> end xilinx; <p> But I found these
errors at implementation steps : <p> Error   L-3/C0 : #0 Error: <BR>
&nbsp;:/Xilinx/active/projects/and3_gat/readback.vhd  line <BR>
&nbsp;-3   Library logical name VIRTEX is not mapped to a <BR>
&nbsp;host directory. (VSS-1071)  (FPGA-hci-hdlc-unknown) <BR>
&nbsp;&nbsp;Error   L4/C0 : #0 Error: <BR>
&nbsp;E:/Xilinx/active/projects/and3_gat/readback.vhd  line <BR>
&nbsp;4   No selected element named COMPONENTS is defined <BR>
&nbsp;for this prefix.  (VSS-573) <BR>
&nbsp;&nbsp;Error   L13/C0 : #0 Error: <BR>
&nbsp;E:/Xilinx/active/projects/and3_gat/readback.vhd  line <BR>
&nbsp;13   The intermediate file for entity RDBK is not in <BR>
&nbsp;the library bound to WORK.  (VSS-1084) <p> What do they mean ? I really
apreciate the feedback <BR>
&nbsp;from all of you. <p> Regards <p> Nyoman Yani

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