Dear all I am using Xilinx Foundation 3.1i to implement my design into XSV board and debug using hardware debugger. I am trying to instantiate readback symbol in my design using this file : library IEEE; use IEEE.std_logic_1164.all; library virtex; use virtex.components.all; entity rdbk is port ( rt, clk : in STD_LOGIC; rd, rip_p : out STD_LOGIC ); end rdbk; architecture xilinx of rdbk is begin U0: RDBK port map (TRIG => rt, DATA => rd, RIP => rip_p); U1: RDCLK port map (I => clk); end xilinx; But I found these errors at implementation steps : Error L-3/C0 : #0 Error: :/Xilinx/active/projects/and3_gat/readback.vhd line -3 Library logical name VIRTEX is not mapped to a host directory. (VSS-1071) (FPGA-hci-hdlc-unknown) Error L4/C0 : #0 Error: E:/Xilinx/active/projects/and3_gat/readback.vhd line 4 No selected element named COMPONENTS is defined for this prefix. (VSS-573) Error L13/C0 : #0 Error: E:/Xilinx/active/projects/and3_gat/readback.vhd line 13 The intermediate file for entity RDBK is not in the library bound to WORK. (VSS-1084) What do they mean ? I really apreciate the feedback from all of you. Regards Nyoman Yani