FFT using logic gates only

You'll probably have to do it manually, and perhaps ask yourself why you want to do it.

FPGAs aren't actually built from these primitive logic gates but rather LUTs and FFs, so there's no reason for the tools to deal in any constructs other than these.

Joel

In any case, with the FFs in there for free, there is no reason not to pipeline it. Look up systolic array processor.

-- glen

The technology schematic is not that high level - it shows you look-up tables!

Presumably, it also shows you some use of MUL18 blocks - but that's what the FPGA has available.

If you really want to see it as a mess of gates, you'll have to synthesize with some ASIC tools which target actual gates rather than FPGA elements.

I'm not sure what you gain from that though?

Cheers, Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

You can't remove your state information (i.e. flip-flops) unless you design without them. Which would be ... interesting, I would like to see your Fmax.

I am pretty sure in ISE (xst) you can output the structural Verilog. This should be the low-level unmapped view. As mentioned, because it is FPGA specific synthesis you probably will have some FPGA specifics, example FPGA multiplies.

You can do generic synthesis with Icuras (quality??). You can get a generic netlist.

Chris

CLEARLY, this is a homework question of some kind, that's the only reason someone would do this. And, the person who invented the question apparently doesn't know how FPGAs are actually built or configured, as the question seems nearly idiotic. it would be QUITE difficult to force the tools to avoid using any FFs. If it really ISN'T homework, then it is from the same camp as the guys who build digital clocks from vacuum tubes or computers from discrete transistors.

Jon

implementation

SNIP!

is

If homework: malice; otherwise stupidity.

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I am thankful to you guys especially Martin and glen , I used Xilinx schematic editor to build the 2d 8*8 DCT using Look up table with adders and few multipliers. It is synthesized and it performs accurately on lena.jpg and results are pretty good as compared to matlab. this is our first step and using IC fabs technolgy we are set to implement the same thing on MTJ's by the way RCIngham when you invent new technology you have to go to basics. e.g CAN YOU EXPLAIN ME THE MULTIPLIER ,FF and other stuff in magnetic gate MTJ's . if still clueless here is a paper which i am using

A High-Reliability, Low-Power Magnetic Full Adder Yi Gang1, 2, Weisheng Zhao1, 2, Jacques-Olivier Klein1, 2, Claude Chappert1, 2, Pascale Mazoyer3

1IEF, Univ. Paris-Sud, Orsay, 91405, France 2CNRS, UMR 8622, Orsay, 91405, France 3STMicroelectronics, 850, Rue Jean Monnet, 38926, Crolles, France

.

So, this wasn't targetting any FPGA technology at all, and therefore the thread is completely off-topic for the newsgroup...

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Any what exactly is wrong with vacuum tube digital clocks, or discrete transistor computers, if that is what one considers fun or interesting?

Rather than suspect a homework problem, or feeling the need to insult the OP's question, I wonder if it's just the curiosity factor of a person new to electronics, who has put together the ideas of "FFT=interesting" and "logic gates = makes stuff happen" and wondered "how can you make an FFT using logic gates?"

This sort of questioning should be encouraged, with the answer consisting of both what the drawbacks would be of attempting such an approach, as well as suggesting a look at how modern implementations of the FFT in hardware are done.

--
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