How to locate a net in the design

'XLXI_7_XLXI_1/BU199' has unconnected output

You may be able to locate it down to the COREgen module it's in, but unlikely to "fix" the problem. I generally ignore these messages. Very informative names starting with BU are a mark of Xilinx COREgen designs. These often end up with unconnected innards that are ripped out at mapping time. One thing that can cause this is generating odd width FIFO designs using block RAM (e.g. using 27 bits of a 36-bit block RAM).

The problem with trying to fix this is that you can't easily modify the internals of the COREgen module, so if you can't find the right settings to generate a module without the errors you might as well live with the warnings.