Hi
I am using synplify to synth a design with some xilinx core gen devices. get warnings on some of the core gen edif files stating that there is a interface mismatch between the verilog and the edif. I can only assum that it is something that core gen is not doing correctly. Has anyone els seen this problem? Here is the warning I get.
@W: : | Interface mismatch for Entity/Module dplbuf_16x512