hi :
I got another problem. I want to see the internal signal inside a design but the result is not waht i want .
I just simulate a distributed selectRAM generated in ISE. And I want to see the signal before reaching the output pads of the viretex II fpga.i.e. just the right output port of the distributed selectRAM.
I found these net names in fpga editor and add them to modelsim waves, just to find that they are the same with the output port of the IO pin. Are they should be the same? I just want to see the timing excluding the IOB delay.
I hope I explain my problem clearly. thanks everybody.