How can I have multiple drivers of one inout port?

Hi,

I am trying to connect the bidirectional ports of two components to one bidirectional set of pins on my FPGA. Is it possible to do this in VHDL? The following example does not appear to read the bidir port:

entity whatever port ( signal choice : in std_logic; signal my_bidir : inout std_logic ); end;

architecture rtl of whatever is

signal x0_bidir, x1_bidir : std_logic;

begin

xInstOne : x port map ( my_bidir_port => x0_bidir );

xInstTwo: x port map ( my_bidir_port => x1_bidir );

my_bidir