Hi, Just to learn VHDL, I cannot understand a problem with the example stopwatch VHDL coming with Xilinx webpack 8.2. In the source window, Inst_dcm1 and XCOUNTER have a red question mark even though I can see there are "dcm1.vhd" and "tenths.vhd" and their module files in the folder. How to attach the respective files to the design? The following is from the readme txt file.
- DCM1 -A single DCM clocking module created with Xilinx Architecture Wizard.
- DECODE -HDL-based macro. This macro converts a binary input to a one-hot output.
- TENTHS -A Coregen 10-bit, one-hot encoded counter.
BTW, in which manual talks about the topic?
Thank you in advance.