help with Design Compiler -> Quartus

Can you give one or two examples of such components? It may be that these are Altera primitives which are known to the Quartus software.

Best regards,

Ben

On 30 Jan 2007, you wrote in comp.arch.fpga:

I solved one of my problems. Because I'm new to this whole topic I did't know that I have to use a .lmf file. So now I almost mapped all of the components like ABTL ... and so on. But still there is on which I do not get mapped. It's a component called DFFS. I don't know why this one doesn't get mapped. Because in the .lmf file it says

FUNCTION "DFFS" ("D","CLK","VDD" ,"VDD") RETURNS ("Q") END

BEGIN FUNCTION dffe (D,CLK,CLRN,PRN,ENA) RETURNS (Q)

so it should work.

because the used component has the following port map structure

D: IN std_logic; CLK: IN std_logic; Q: OUT std_logic;

I could create a D Flip-Flop by my one with the help of Quartus Megafunction to make it work, but thats not the way it should go.

Could you please help me?

Sebastian

Is there some reason you don't want to synthesize the original source code in quartus, instead of importing the netlist? Quartus will undoubtedly do a better job of synthesizing to the altera fpga architecture than design compiler will.

Andy

On 05 Feb 2007, you wrote in comp.arch.fpga:

Yes, the reson why I use the design compiler (better to say I use a gui which sits on top of it. called coreConsultant) is because it is a designware source which is encrypted.

It sounds like you have a vendor netlist for Synopsys libraries, not source code.

Buy the source code or write your own.

I would not expect that a black box by Synopsys would work with any tools not specified by Synopsys.

-- Mike Treseler