Selecting FPGA synthesis, place and route and simulation tools

Hi,

We're considering using the Xilinx Spartan FPGA series. We plan to use the free Web ISE tools for doing our verilog synthesis, place and route and simulation. I have several questions about this. I'm assuming that synthesis and pnr are well taken care off by the Web ISE. However, I noticed simulation might have to be done using ModelSim and rather than being free it is provided only with time limited licensing. Are there alternatives to ModelSim? We used to use Cadence's ncsim but we will not have funding to use it anymore. We were using verilog and C testbenches through PLI to get coverage in our simulations. I'd like to hear about what other people and teams have experienced in this area. This work is not-for-profit.

Thanks, R. Beresford

Reply to
rod.beresford
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Have you looked at iverilog

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Peter

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Reply to
Peter TB Brett

The Modelsim supplied with Webpack is not time-limited :

From the Webpack FAQ :

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"The limits for Modelsim MXE-III Starter are 10,000 lines of debuggable code. Beyond this limit, the processing begins to slow down, but does not stop. The usefulness of this software is going to depend on coding style and type of simulation (either functional or timing) that is desired."

Xilinx have introduced their own simulator in ISE 7 but I don't think it comes with Webpack (yet?)

Reply to
Mike Harrison

Yes, I had heard about it and the GEDA suite. The general perception I got was that it's not yet ready for prime time. Is that a fair assesment? If there are people using it for real projects and able to integrate it with PLI testbenches and such, then please by all means let me know. Thanks.

Reply to
rod.beresford

Well, I just used gschem/gnetlist for a 700-component board I just had made (which I'm currently writing the FPGA cores for).

We use VHDL in our shop, so I can't help out telling you about iverilog. How about you just download it and try it out?

Peter Brett

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E-mail:  peter@peter-b.co.uk
Website: http://www.peter-b.co.ukv2sw6YShw7ln5pr6ck3ma8u7Lw3+2m0l7CFi6e4+8t4Eb8Aen4g6Pa2Xs5MSr5p4 hackerkey.com
Reply to
Peter TB Brett

I use Aldec's Active HDL, I find it more ergonomic than modelsim, and it has a very nice design entry suite as well. The editor is emacs-like, but also has the ability to copy and paste VHDL declarations and both VHDL and Verilog instantiations of any of the library components as well as any of your own components that have been compiled. It also has a block diagram viewer/editor, matlab co-simulation and combined verilog/vhdl/edif simulation. I highly recommend this product if you are looking for an alternative to modelsim. I think you'll be very happy with what you see if you check it out.

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--Ray Andraka, P.E.
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Reply to
Ray Andraka

Is all this free? for Linux also?

Reply to
Preben Holm

No, it is not. I thought you were looking for alternatives to modelsim PE, not for free simulators. Please forgive me.

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--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Reply to
Ray Andraka

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