WebPack - mixed design flow

My system has netlist in EDIF while some of technology elements used in the netlist are described in a separate VHDL file at logic level. WebPack supports only pure EDIF, schematic, Verilog or VHDL design flows. Is ther a way to compile a mixed design? That is, I first elaborate VHDL and then load EDIF netlist which uses VHDL components.

May be ISE Foundation supports this?

Reply to
Valentin Tihomirov
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Steve Lass

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