Questions about Design Compiler.

Hi,

I'm new to Synopsys Design Compiler. I have some questions:

1. Should I always set drive strength and load driven by the ports before optmization? But I don't know what kind of value i can use and how to get the value? for drive strength and load?

1. Should I always set input_delay and output_delay? In the tutorial manual of Synopsys Design Compilefr, it only set output delay to the Clock? Why don't we need to set input_delay?

2. After I compiled my design, and I found slack time for all end-points are zero? Is this correct?

Thanks.

Liang