MIG help (Virtex-6)

Hi

I have created a controller for DDR3 with the MIG. The MIG output folders are example_design and user_design. according to MIG report :

" - example_design: This folder includes the design with synthesizable test bench.

- user_design: This folder includes the design without test bench modules. "

But actually i don't see any important difference between these folders except the name of some files! The top module of both folders have instantiated the controller and the traffic generator for testing. So which module is appropriate for start of my design?! Both are too complicated that i can't use in my design!

Any hint please?

Thanks in advance

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spman
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On 1/1/2013 1:24 PM, spman wrote:> Hi > > I have created a controller for DDR3 with the MIG. The MIG output folders > are example_design and user_design. according to MIG report : > " > - example_design: > This folder includes the design with synthesizable test bench. > > - user_design: > This folder includes the design without test bench modules. > " > > But actually i don't see any important difference between these folders > except the name of some files! The top module of both folders have > instantiated the controller and the traffic generator for testing. So which > module is appropriate for start of my design?! Both are too complicated > that i can't use in my design! > Any hint please? > > Thanks in advance > > --------------------------------------- > Posted through

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Here are the differences between the designs

example_design

-------------- The memory tester components along with the MIG are collected into a top level module, example_top.vhd, that is in the ip_top folder. The top level test bench, ui_top in the sim folder only instantiates one DUT (Device Under Test) module, example_top. The other modules in the test bench are memory and wire models needed to complete the test bench.

There are two status outputs from example_top - phy_init_done and error

- and these indicate when memory calibration has successfully completed and when an error has occurred in the memory test.

example_design can actually be run through the Xilinx tools and the resulting bit stream can be used to verify that the memory is actually working on the board. You can connect the phy_init_done and error signals to LEDs on your board and use this to verify that the memory is working. To verify that the memory test is working, random memory pins can be shorted to ground with a low value resistor and the error LED should turned on. NOTE: The error signal is latching, so the design must be reset to clear the error!

user_design

-------------- The top level DUT for this design is the mig_ddr3 module from the ip_top folder. The sim_tb_top.vhd module instantiates this, as well as the memory tester modules and wire and memory modules.

You will probably want to use mig_ddr3 as your top level, because it has the interface to the user's application code as well as to the memory chips/modules but doesn't have any memory test logic.

If you want to have the capability for memory testing in your design, you can add this buy combining the init_mem_pattern_ctr and mcb_traffic_gen modules into a single module, following the connectivity in the test bench. Then mux the memory tester module and your application code into the mig_ddr3 module.

Good luck, Paul

Reply to
Paul Urbanus

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