Hello,
I am currently using the DDR2 controler from XILING (under MIG1.72) for a VIRTEX4. I am encountering a problem of access speed when I write to the memory. Each time I access the memory, my project requires that I use different line and column addresses (ie. I am writing in different lines and columns each time ). Example: first Write access (address) : line 1, column 1 second Write acces (address) : line 2, column 3
Can you indicate me how to use the controler in an optimal way (how can the delay between the 2 write access be minimized) ? Should I use the 'PRECHARGE' command ? Can I use a option in MIG ?.
Please, find below Datasheet generated by MIG Version 1.72
I would be grateful if someone could help me. Thanks in advance
Regards, Benoît
---------------------------------------------- Datasheet generated by MIG Version 1.72 :
---------------------------------------------- FPGA : Target Device : xc4vlx60-ff668 Speed Grade : -11 DCI for Data : enabled DCI for Address and Control: disabled
Interface Parameters : Frequency : 200 Data Width : 16 Depth : 1 Row Address : 13 Column Address : 10 Bank Address : 2 ECC : ECC Disabled
Other Options : DCM : enabled Add Test Bench : disabled Clocking Type : Direct_clocking ClockCapableIO(CC) : disabled
Design Parameters : Mode Register : Burst Length : 4(010) Burst Type : sequential(0) CAS Latency : 3(011) Mode : normal(0) DLL Reset : no(0) Write Recovery : 3(010) PD Mode : fast exit(0) Extended Mode Register : DLL Enable : Enable-Normal(0) Output Drive Strength : Fullstrength(0) RTT (nominal) : RTT Disabled(00) Additive Latency (AL) : 0(000) OCD Operation : OCD Exit(000) DQS# Enable : Enable(0) RDQS Enable : Disable(0) Outputs : Enable(0)
Memory Configuration : DDR2_SDRAM:Components Part Number : MT47H32M16XX-5E ********** I used the default MT47H32M16XX-5E model (included in Mig), but I use a ELPIDA EDD5116AFTA (32Mx16) on my board **********