DDR2 controler

Nov 28, 2007 2 Replies
B

Hello,



I am currently using the DDR2 controler from XILING (under MIG1.72) for a VIRTEX4. I am encountering a problem of access speed when I write to the memory. Each time I access the memory, my project requires that I use different line and column addresses (ie. I am writing in different lines and columns each time ). Example: first Write access (address) : line 1, column 1 second Write acces (address) : line 2, column 3



Can you indicate me how to use the controler in an optimal way (how can the delay between the 2 write access be minimized) ? Should I use the 'PRECHARGE' command ? Can I use a option in MIG ?.



Please, find below Datasheet generated by MIG Version 1.72



I would be grateful if someone could help me. Thanks in advance



Regards, Benoît



---------------------------------------------- Datasheet generated by MIG Version 1.72 :



---------------------------------------------- FPGA : Target Device : xc4vlx60-ff668 Speed Grade : -11 DCI for Data : enabled DCI for Address and Control: disabled



Interface Parameters : Frequency : 200 Data Width : 16 Depth : 1 Row Address : 13 Column Address : 10 Bank Address : 2 ECC : ECC Disabled



Other Options : DCM : enabled Add Test Bench : disabled Clocking Type : Direct_clocking ClockCapableIO(CC) : disabled



Design Parameters : Mode Register : Burst Length : 4(010) Burst Type : sequential(0) CAS Latency : 3(011) Mode : normal(0) DLL Reset : no(0) Write Recovery : 3(010) PD Mode : fast exit(0) Extended Mode Register : DLL Enable : Enable-Normal(0) Output Drive Strength : Fullstrength(0) RTT (nominal) : RTT Disabled(00) Additive Latency (AL) : 0(000) OCD Operation : OCD Exit(000) DQS# Enable : Enable(0) RDQS Enable : Disable(0) Outputs : Enable(0)



Memory Configuration : DDR2_SDRAM:Components Part Number : MT47H32M16XX-5E ********** I used the default MT47H32M16XX-5E model (included in Mig), but I use a ELPIDA EDD5116AFTA (32Mx16) on my board **********


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H

Hi,

did you notice that you always burst in data. So depending on the burst length you have to increment your column address by 4 or 8 to nor overwrite your recent data. Using long bursts increases your performance because your memory wasts much time when you switch between read and write mode.

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N

Not sure if this will help you but the Virtex-5 DDR2 controllers have a feature called Bank Management which improves the management of open banks in your controller.

The controller keeps track of whether the bank being accessed already has an open row or not and also decides whether a PRECHARGE command should be issued or not to that bank. When bank management is enabled via the MULTI_BANK_EN parameter, a maximum of four banks/rows can open at any one time. A least recently used (LRU) algorithm is employed to keep the three most recently used banks and to close the least recently used bank when a new bank/row location needs to be accessed. (From MIG UG)

This is not going to be added as a feature in Virtex-4 controllers, but you can generate a Virtex-5 controller and implement it on a Virtex-4 device at the cost of a drop in overall performance. But it is likely that it will improve the delay between different writes (if they are issues to a open bank).

Just a though, Good luck Jaco

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