hi all: I have a question about stratix II .An oscillator must drive a constant clock frequency to an FPGA pin. The maximum frequency limit depends on the speed grade of the FPGA. Frequencies of 50 MHz or less should work for most boards.If my oscillator is less than 50 MHz ,how to work about this system ? If about PLL ,I want to know how dose PLL work.
- Does PLL function automatically or need manual configure to initial PLL in the system?
- Dose PLL reference anything or any paremeter to lock the frequency? What is the paremeter? Thanks in advance.