Channel Link signals into Xilinx

or

Both Virtex-II Pro and Spartan-3 support LVDS signals. I don't have a Spartan-3 specific design but here's an example of one such product using Virtex-II.

Essentially, Channel Link is a 7:1 LVDS interface with a 66 MHz input clock. Use the CLKFX and CLKFX180 outputs from a DCM. Set the CLKFX_MULTIPLY=7, CLKFX_DIVIDE=2. Use DDR flip-flips and LVDS input or output buffers for either the input (receiver) or output (transmitter). 66 MHz * 7/2 * 2X (DDR) = 462 Mbps.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

--------------------------------- Spartan-3: Make it Your ASIC

Hi Steven,

It would appear from this article that the designer used another chipset to do the Camera Link interface and not the IO pins of the Virtex directly. This is contrary to what I am thinking about. However, considering what you are saying, it does seem possible that the link can be done directly with either Virtex or Spartan3 IOs, although I haven't found anybody to tell me that they actually have.

clock.

Yep, we've done that with Camera Link into a V-II (not Pro, but that shouldn't matter)

There's an appnote (XAPP265) on doing (de)serialisation which as a very CameraLink looking appendix to it.

Cheers, Martin