I have to connect a dual 12-bit ADC with serial LVDS outputs (2-lanes per converter) to a spartan 6 FPGA. It would be ideal if I can use a single HDMI connector for this.
The converters I'd like to use are the ADS6224 or ADC12S105, running at
100 MHz sample rate. They have 6 data LVDS data outputs: 4 data lines, 1 frame clock and 1 bit clock.Since the HDMI connection only has 5 differential pairs (including the HEC data lines) I had the idea to not connect the bit clock, but instead use the FPGA's DCM to reconstruct the bit clock from the frame clock.
Any comments on this idea? Could that work?
Thanks, Thomas