Hi all,
Been reading a lot from the archives about synch/asynch resets. Found lots of good stuff and am now more enlightened.
My conclusions so far:
(1) Use synchronous reset in general on the flip flops for FPGAs
(2) If system requires asynch reset on the flip-flops, synchronise the release of the reset to the appropriate clock domain to avoid the release spanning a clock edge due to fanout delay.
Question 1: I guess the main reason for using an asynch reset is for when the circuit must be reset in the absence of a working clock? If so, how can the release ever be synched to said clock if it is not working? Hence, why ever use asynch reset on a clocked circuit?
Question 2 (the main one): In general it seems the best idea is to use a synchronous reset i.e.:
if (clk'event and clk = '1') then if (rst = '1') then // do reset else // synchronous logic end if; end if;
The question is to do with the source of the rst signal. Assuming that the rst signal pulse comes into the device via a pad, I assume that the circuitry external to the FPGA generating the pulse *must* do so synchronously to clk? (clearly if rst is generated on the device synchronous to clk then no problem). Otherwise, if rst is asynchronously generated, there must be a chance of the rst pulse transitioning too close to a clk edge at the flops and causing metastability? Or does this metastability issue only apply for the D/Q pins on the flop?
Thanks in advance for your time,
Ken