When I use xilinx webpack (the latest version, version 6?) to compile my VHDL code, I get this warning message: "WARNING xst737: found 1-bit latch for signal ABC" The code is like this,
process (HOST_WR, HOST_DATA) if HOST_WR = '0' then ABC
explicitly define latch to avoid WARNING in xilinx webpack?
Oct 29, 2004
2 Replies
Stick xilinx latch coding style into Google. Click on the second hit. Syms.
Syms suggests-
thanks for the link to a good reference and you didn't say - RTFM !
the short answer is- complete the if statement - add -
else ABC
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