Confusing Xilinx Webpack warning

When I synthesize the following test code in Webpack 5.1 I get the following warnings. Am I misunderstanding something here? Note that the code below is a silly example as I tried to simplify my actual code to understand the warning by removing parts that don't cause the error.

WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used.

module test(a,b,c,d); input [1:0] a, b; output c, d;

reg c, d; reg e, f, g, h;

always@ (a or b) begin e = a[1]; f = a[0]; g = b[1]; h = b[0];

c = e ^ g; d = f ^ h; end

endmodule

Reply to
Prasanth Kumar
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It's possible that the verilog mapper rewrites the assignments to c & d so that they refer to a & b directly so e, f, g, h are not used to calculate c & d and they are not used any where else either so the warning.

Muzaffer Kal

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ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Reply to
Muzaffer Kal

This kind of warning can happen if 'c' and 'd' turn out not to be used (perhaps due to logic trimming by the synthesizer). If 'c' and 'd' get trimmed then to the synthesizer it looks like 'e','f','g' and 'h' aren't being used and it spits out that warning. Check the logic that 'c' and 'd' drive to see if there's some way those signals might be trimmed.

Rob

Reply to
Robert Finch

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