Xilinx webpack map/route questions

"vax, 9000" a écrit dans le message de news: d1a050$902$ snipped-for-privacy@charm.magnus.acs.ohio-state.edu...

NO, If you want to use global clock network you should infer a global clock buffer (bufg) component ,

I'll add my view for all your questions:

non-clock

Of the recent Xilinx FPGAs, I'm only aware of the Virtex-4 as having the global clock signals available as logic inputs. The other families only allow the physical global clock lines to feed clocks (perhaps also clock enables and resets, I forget what I last saw in the FPGA Editor tool). The software expects that your signal is either a clock or it isn't and tries to gear up for the one or the other.

Because the tool sees "a" clock that it's trying to treat as a clock, it wants to throuw in the BUFG to get onto the clobal clock lines. But you want logic.

The signal gets routed through the BUFG to go to the one item that's clocked. I've seen a mixed-use signal jump off at the input to the BUFG and go to the rest of the logic from there rather than routing normally. That's not necessarily how things are done now.

certain

Try the synthesis directive BUFFER_TYPE (set to "none") to force your clock to be understood as a non-global.

glad to (try to) help,

- John_H

I did not assign any pins. I just let the software to give a free run, and it automatically infered a global clock buffer for my HOST_WR input (supposed to be connected to a CPU WR\ pin).

vax, 9000

Never, never, gate your clock. Ie, always use

process (HOST_WR) begin if HOST_WR'event and HOST_WR='1' then if HOST_CS = '0' then

rather than

HOST_CS_WR > REG

Thanks. I have changed the design to follow this rule.

vax, 9000