I am trying to use a CPLD as a bus decoder and also have the device latch 6 bits of data back to the host via a shared data bus. I cannot get this code to simulate, using Xilinx Webpack. I have asked the local Xilinx FAE for help but he is not versed in VHDL. This can't be as difficult as it seems... nobody would be using these devices. I am getting the following signal for most all of the signals that I have declared. I have patterned my code after one of the examples included in WebPack(Xilinx software).
WARNING:Xst:646 - Signal is assigned but never used.
I have included my code... it is not that large. I would appreciate a kick in the right direction.
Thanks, David Thurlow
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- DESCRIPTION:
-- Decode/Respond to specific addressed commands
-- from the Host, via the BUS.
-- The commands control the FIFOs... READ/WRITE and
-- also send Status Bits back to the Host.
--
--
-- ************************************************************
entity decoder is Port (ADDR : in std_logic_vector(9 downto 0); -- ADDRESS BUS D : out std_logic_vector(5 downto 0); -- OUTPUT BITS 6 OF THEM N_GWR : in std_logic; -- BUS WRITE PULSE N_GRD : in std_logic; -- BUS READ PULSE N_DRV_ENAB: out std_logic; -- ENABLE THE 245 DRIVERS PCK_READY: in std_logic; -- MESSAGE TO HOST READY DIR : out std_logic; -- DIRECTION SEL FOR 245 DRIVERS IN_FIFO_EMPTY : in std_logic; -- FIFO EMPTY SIGNAL OUT_FIFO_EMPTY : in std_logic; -- FIFO EMPTY SIGNAL N_RST_IN : out std_logic; -- RESET IN FIFOS N_RST_OUT : out std_logic; -- RESET OUT FIFOS N_RST_SYS : in std_logic; -- MASTER RESET N_X_RD : out std_logic; -- HOST READS THE FIFOS N_X_WR : out std_logic; -- HOST WRITES TO FIFOS FIRST : out std_logic; -- SET BIT 9 IN FIFOa... 1st BYTE LAST : out std_logic; -- SET BIT 9 IN FIFOb... last BYTE G_BUS_ACTIVE : out std_logic; -- LIGHT LED DURING HOST CMDS TRI_STATE : out std_logic; -- CONTROL GTS1...address selected TRI_STATE_IN : in std_logic); -- CONTROL TRI-STATE OUTPUTS end decoder;
architecture Glonet_Decode of decoder is -- the READx and WRITEx signals will be set when a proper -- address and either /GRD or /GWR are active. They will be -- cleared when /GRD or /GWR are inactive. signal DAT_OUT : std_logic_vector(5 downto 0); -- STORE STATUS FLAGS signal READ0 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND /GRD signal READ1 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND /GRD signal WRITE0 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND /GWR signal WRITE1 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND /GWR signal WRITE2 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND /GWR signal WRITE3 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND /GWR begin
process(N_GRD, N_GWR) -- THESE SIGNALS ARE THE TRIGGER FOR ANY ACTION
begin -- IF A READ WAS COMMANDED, CHECK THE ADDRESS. -- ONLY RESPOND TO SPECIFIC ADDRESSES. -- SET 'FUNCTION' FLAG AND BUSY FLAG if N_GRD'event and N_GRD = '0' THEN -- IF HOST READ AND NOT BUSY case ADDR is when "0001110000" => -- IF 1C0h READ FIFOs READ0 -- IF 1C1h READ THE STATUS FLAG LATCH READ1 -- READ PULSE NOT FOR US, IGNORE IT end case; END IF;
if N_GWR'event and N_GWR = '0' THEN -- IF HOST WRITE AND NOT BUSY case ADDR is when "0001110000" => -- 1C0h WRITE TO FIFOs WRITE0 -- 1C1h WRITE TO FIFOs WRITE1 -- 1C2h WRITE TO FIFOs WRITE2 -- 1C3h RESET FIFOs WRITE3 -- WRITE PULSE NOT FOR US, IGNORE IT end case; END IF;
if N_GRD = '1' and N_GWR = '1' then -- NOTHING HAPPENING ON BUS N_X_RD