I new idea?
What do you experts think of the following entity I wrote? It?s purpose is to eliminate metastability of the q signal.
The d signal is synchronous to a 1.8 MHz clock and the q will be synchronous to a new 24 MHz clock. That means that at worst the entity will sample ?one? meta stable bit-value surrounded by many non meta stable bits.
For example (sampled values)
d: 00000X111111X00000X111111X00000 (X = meta stable bit-level)
From the initial state it need to interpret two neighbor samples as ones, only then it gives a one on the q output. Then after that to get a zero on the q output it must interpret two neighbor samples as zeros, then it gives a zero on the q output.
And if you don?t think it will work please explain why. :-)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync_to_new_clock is
Port ( new_clk : in std_logic;
d : in std_logic;
q : out std_logic);
end sync_to_new_clock;
architecture beh of sync_to_new_clock is
signal state : std_logic := '0';
begin
process(new_clk)
begin
if rising_edge(new_clk) then
case state is
when '0' => if d = '1' then -- a "real" 1 or a "fake-mata-stable" '1'
state