Meta-stable problem with MAX-II ?

I suspect that there is something else that you're not quite telling us and that the problem is that the setup time is being violated on some 'other' logic that is causing the pulses to be missed.

In other words, if the 90ns pulse signal is 'D' and the output that gets 'missed' is 'Q', then does 'D' feed into ANY logic other than that for 'Q'? Like a state machine perhaps? If so, then whatever that other path(s) is is probably getting whacked out because of the setup time violation.

To check this look at your fitted design in the Quartus Technology Map viewer and verify that 'D' is only an input to the flip flop that compute 'Q'.

KJ

Can you post a sample design? Nowadays FFs, even when they go metastable, will only get into that state for a very brief time.

Assuming the incoming pulse is asynchronous to your system clock, I'd say something like this should do the trick:

entity snagpulse is port ( clk : in std_logic; rst : in std_logic;

pulsein : in std_logic; snagged : out std_logic ); end snagpulse;

architecture justtoillustrate of snagpulse is signal FF1, FF2, FF3; begin

-- Sync the incoming pulse to the system clock process(clk) begin if rising_edge(clk) then FF1

Hmmm... Seem to have forgotten the bits where snagged is set to '0' again - I'll trust everyone's intelligence to add the appropriate two statements.

Best regards, Ben

set to '0' again -

Peter Alfke schrieb:

so it looks!

BTW, there is an "A" in your name too ;) uups in mine too

Antti

Thanks for the inputs so far! Here's the code that's giving me greif:

architecture inside of stepmachine is

type pulsestate is (IDLE, PAUSE, OUT1, OUT2, OUT3); signal currentstate, nextstate : pulsestate;

signal stretched : std_logic;

begin

process(CLOCK, RESET) begin if(RESET = '1') then currentstate

Xntti, Mr Xlfke,

You've got a definite knack for it - maybe you should apply for a job in Altera apps - I think they would be most happy to receive you ;-)

Well, what I've written pretty much does this (once you've added the "else snagged

Assuming that "CLOCK" is your 16 MHz clock, and "pulse" is your 90nS pulse, then it is no surprise at all that this design is failing. The problem is you don't have a synchronizer on the signal "pulse". Depending on how pulsestate is encoded, multiple flipflops could change in this piece of code at the indicated line

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