how to filter glitches and mutliple transitions?

Hi Frank

You are describing a soft filter.

I have a number of them in a current design (it's in a rather noisy environment) and I use a 5 bit counter as part of a state machine.

I assume you have an appropriate clock, so simply qualify the signal as continuously present (or perhaps mostly present) for the 3us you state.

With a 10MHz clock, for example, a 5 bit counter is almost perfect (and besides, we can always terminate at count = 30 ;)

I like your approach, but this is simple and uses pretty limited resources.

so, somewhere

wire Sig; // the signal we are watching reg SigValid; // valid indicator reg [4:0] SigCount;

always @(posedge clk) begin if (!Sig) begin SigCount

// fix the next line // was else if (SigCount == 28) else if (Sig & SigCount == 28)

// qualify signal properly

Yes, that's a saturating counter. You have one minor blindspot in your topology, if you merely use the MSB as the output, it can spin quite quickly if the pattern makes your counter go 01111 / 10000 / 01111 / 10000

So, better is to take something like the saturating sense logic (which has to already be there), and feed a JK FF, or SyncSET/SyncRST

-jg

maybe this is sufficient, but this solution won't filter negative glitches. See below for my try, with hysteresis (thanks Jim for the blindspot). I wonder if it is overkill :-)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL;

entity low_pass_filter is generic( counter_max: positive := 30; hysteresis: positive := 5); port( clock: in std_logic; reset: in std_logic; input: in std_logic; output: out std_logic); end entity low_pass_filter;

architecture rtl of low_pass_filter is

constant low_limit: natural := (counter_max - hysteresis) / 2; constant high_limit: natural := low_limit + hysteresis;

signal counter: natural range 0 to counter_max := 0; type state_type is (low, high); signal state: state_type := low;

begin

filter: process(clock) begin if reset = '1' then counter

Some corrections: hysteresis doesn't make sense. I've deleted it and tested in low-state for counter=counter_max and in high-state for counter=0 and tested it today with real hardware and it works.

Well, good!

If talking through a problem helps you solve it, only too glad to talk :)

Cheers

PeteS