xilinx sync fifo with first word fall-through

May be it's not pretty, but i'm using this for quite a while. I'm creating wrapper for the fifo and this component.

-------------------------------------------------------------------------------

-- Special entity "auto_first_read"

-- provide loading output register with first word, as soon this first word comes to Fifo. It forms additional

-- RdEn pulse and take care of proper "Empty" signal.

--------------------------------------------------------------------------- LIBRARY ieee; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;

------------------------------ library work; use work.types.all; use work.components.all;

--------------------------------------------------------------------------- ENTITY auto_first_read IS port ( RdEn: in std_logic; RdCe,RdClk: in std_logic; Ainit: in std_logic; Empty: in std_logic; RdEnOut: out std_logic; EmptyOut: out std_logic); END auto_first_read;

ARCHITECTURE arch OF auto_first_read IS

--------------------------------------------------------------------------- signal iNextState : integer; signal iAutoRdEnOut,iStrobRdEnOut,iEmptyOut: std_logic; begin

---------------------------------------------------------------------------

-- This process forms "iAutoRdEnOut"- additional pulse to pass data to output pipeline reg

-- and "iEmptyOut" - delayed ver of "empty" signal from asyncfifo process (Ainit, RdClk ) begin

if (Ainit='1') then iNextState

leevv schrieb:

{code snipped}

looks like exactly what I needed, tried last night the same but failed with first attempt

sposiba ogromnoje!

Antti PS I wonder how many xilinx users have made or have needed this auto_read_first FIFO fix? really simple thing, but not available with coregen

Pojalujsta. ;-)

Why only xilinx. I'm just currious is it standard feature somewhere else (A or L)?

Peter Alfke schrieb:

Peter

I feel really stupid - I had to target S3e, but I dont have any nice s3e boards around so I tested on the board that is closest to the keyboard, what happens to be ML501.

So somehow looking at the x markings I got the impression that "first word fall through" is not supported by coregen for S3e at all. As Pixel Velocity just told me in email this isnt true. I was too tired eyes hurting too much, didnt see or understand the x's in the coregen screen.

So I have implemented Leew's solution that works just perfectly. After that I have also validated the coregen's solution, that also works, but has a hidden 'issue' namly with coregen FIFO 'empty' flag de-asserts not when WR asserts but when it deasserts! so if 1000 words are written to FIFO then empty goes away then when the WR ends eg at time when there are 1000 words already in fifo. Leews solution doesnt have that issue.

Ok for my current application both alternatives would work ok, but I already had the Leew's fixup in place

Antti

Antti schrieb:

actually i feel less stupid, I did checkout coregen FWFT fifo yesterday, but I used a testbench that writes a burst to the fifo, and I looked in the simulation where the burst starts, and the FIFO output did not change so I assumed the FIFO wasnt working - I did not notice that the coregen FIFO delay its output update and the EMPTY flag de-assertion until the burst ends. this can be at the same time when is completly full, seems like a little bizarre behaviour for an FIFO. for me it was so unexpected that I didnt investigate the coregen FWFT fifo any longer, and implemented the workaround

Antti