EDK problems

Does anyone have experience of using the Altera and Xilinx embedded software? I have been using EDK but I am getting very frustrated with it. It seems that every new release includes a generous helping of bugs. I seem to find myself wasting hours just trying to get a design to be implemented. For example the 14.1 release now seems to have some problems with the interrupt controller, yet it was ok in the previous release. Does the Altera software have as many bugs?

TIA

Jon

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maxascent
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I am not using the very latest Xilinx chip products, so I don't have to use their very latest software. I am using 10.1, as it supports the relatively modern parts I use as well as some of the older parts that are still used in some of our more mature designs. Sometimes funny things happen and I think it is using old versions of the vhdl files, but exiting the Ise environment and starting it up again seems to clear it up. Otherwise, I have had no significant problems with Ise 10.1

Jon

Reply to
Jon Elson

My experience with Altera embedded is limited to taking a short Altera-pres= ented class on their new tools and (of course) it all worked beautifully, w= ith some really nice bells and whistles for debugging and putting together = a quick TCL-base GUI. Since this is in a controlled environment, take it f= or what it's worth...

I can, however, second your frustration with the Xilinx EDK. Every time I = make a change to a peripheral on our design, getting the flow to work again= is always very painful. The tool is very unreliable in how it converts ac= tions in the GUI (XPS) to actual instructions for the platform generator (.= MHS file) and it's often that I/O changes don't show up in the file, and th= at resulting processor no longer works with the debugger, even when you *th= ink* you've correctly regenerated the "base system package" (*_bsp project = in XSDK) and done everything right.

I also burned up 2-3 days when I was new to the environment because the Lin= ux version of XSDK has some GUI quirks that make it unclear which .ELF file= you're loading when you attempt to debug the device with the JTAG cable. = The default file in the pull-down list may show your current compiled progr= am, but it actually loads it with bootloop.elf (do-nothing code) unless you= explicitly pull-down the list and "re-select" it.

We're going to be starting an Altera project within a month or two and I ea= gerly anticipate what kind of "gotchas" we encounter in their tools. I hop= e to be pleasantly surprised.

-- Kev> Does anyone have experience of using the Altera and Xilinx embedded

em

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hdlnerd

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