Hi all,
I have a Spartan-6 LX45 board with a whole bunch of lvds going in and out at a rate of 780mbps. After running out of pins I was forced to put two lvds receiving pairs into a different bank from the rest of the bus. To make matters worse this bank has an active MCB. All of the tx/rx lvds is synchronous with a clock I have inside the fpga so both transmit and receive are handled through the BUFPLL method suggested in XAPP1064. Receive channels are using the differential phase detector mode of IDELAY2 and ISERDES2.
The bank with the MCB presents a unique challenge because the MCB makes use of both BUFPLL resources available along that edge of the device. On the bright side I am able to run the memory interface at the same 780mbps potentially allowing me to use the same BUFPLL technique used on other edges of the device. The problem is that the MCB requires the BUFPLL to be run with DIVIDE=2 essentially causing the fabric side of the ISERDES2 to run at 390mhz!
In the XAPP1064 source code I found the following note relating to the instantiation of ISERDES2:
DATA_WIDTH => 6, -- SERDES word width. This should match the setting is BUFPLL
I wonder what exactly "should" means. Say that I have BUFPLL with divide=2 and ISERDES with width=6. What is really going to happen? Looking at figure 3-1 on page 80 of UG381. It looks to me as though it would work fine. A bitslip machine would be able to line of which of the 3 strobes was actually the correct one.