Hello, I have a little problem, it is about real values in VHDL, and the way = Quartus is managing them. I am describing a simple DSP function (filter) in VHDL to implement on a = Stratix device. As you probabely know, these functions need to shift = input values in a register bank (declared as "signal" in VHDL), applying = coefficients (reals) to them. These signals must therefor be of real = type. Quartus returns this error on compilation : Error (10414): VHDL = error at iir_butterworth_3.vhd(49), at object "X": a real cannot be = non-constant ("X" is such a register) Of course the filter = coefficients (reals) are hardcoded as constants in a package, but these = shift registers containing reals *are not* constants, they of course = have to be signals to enable shifting.=20 I have read about obscure floating point units implemented on Stratix = devices, so I suppose it should be possible to manage real signals = (floating/fixed point representation ?) in it.=20 Does anyone have an idea about how I can use non-constant reals to = create a DSP core on Stratix ? I think it is only a synthesis tool = issue.
Here is the code (no comment on the casts, I *AM* aware this is not the = most elegant) A, B, C and D are the filter coefficients. This description simulates PERFECTLY with Modelsim...
architecture testing of iir_butterworth_3 is
type register_bank is array (0 to 2) of real; signal X : register_bank; signal Y : register_bank;
begin
DSP : process(clock, reset, data_in)
begin
if reset =3D '1' then -- initialise registers to 0 for i in 0 to 2 loop X(i)