block adder for Altera!

look in:

-- Mike Treseler

The next version of Quartus will have a floafting point, addition/subtraction megafunction. It is due to be released in early Q2 of

- Subroto Datta Altera Corp.

thank you very much...but when the new version of Quartus will be released? I'll have my dissertation in april! thanks again Cecilia

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Consider simplifying or delaying your dissertation. A marketing "Q2" means July 1, and learning vhdl any sooner is unlikely.

-- Mike Treseler

hi even i was struggling with floating point calculation in vhdl...a simple search on google landed me on the following website.

i tried the routines in xilnx ise + modelsim...it worked fine.

nisheeth

First, do you really need floating point, and, if so, how big an exponent range do you need? Floating point multiply isn't much harder than fixed point, especially if you have multiply hardware like many FPGAs now do. Floating point add requires a barrel shifter which is pretty big. If you want full IEEE standard there is a lot more logic required.

On many processors floating point is easy and just about as fast as fixed point, so much scientific and engineering programming is done that way. That doesn't mean that it needs to be done that way. Reducing the exponent range will simplify floating point addition somewhat, though you will have to learn something about floating point hardware to do that, and most likely you will anyway.

Though the usual reason for using FPGAs for computation is speed, and I don't believe that EEGs are so fast as to require that speed. You might be able to do what you need in software on an FPGA based processor.

-- glen

The link seems to be broken.

Martin

I've found it anyway...thank you! but with the Quartus II I've many problems to use this package...

Cecilia Annovi

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