I'm trying to increase the speed of my Stratix design and would like to change which FFs are turned on within a DSP block.
The Stratix handbook shows the DSP path something like this:
[ FF ] [ X ] [ FF ] [ + ] [ FF ]where [X] is the multiplier block, [+] is an accumulate block and all registers are optional. I don't use any of the accumulators, and I use pipeline_delay=2 going through the multiplier.
What I find is
(a) Quartus always invokes the first and 2nd FFs, viz
[ FF ] [ X ] [ FF ] [ --> ] [ --> ](b) There's > 1ns interconnect delay getting out from the 2nd FF.
What I'd really like is to try
[ FF ] [ X ] [ --> ] [ --> ] [ FF ]in the hope that this will give me faster overall operation.
But I can't find any way to do this. I've looked at the multiplier tdf and it doesn't appear that the choice of which FFs to implement is brought out to HDL.
What I'd like to learn is :
(i) is the path I've diagrammed above possible in the Stratix hardware ?
(ii) how can I make the software implement this ?
Thanks for any help,
-rajeev-