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Question about reset signal for several DCMs in EDK design.

Hello, I have several DCMs in my design and they are phase synchronized. I generated them respectively in the DLL mode from the system clock. The simulation is fine. But when I put the design on board, it stops working somehow. My guess is that the DCMs aren't locked. When I tried a very simple EDK design with only one DCM and tie its reset port with ground, the design always works. If I tied the reset port to the switch on the board (high active), it always works after configuration. But if I push the switch on the board, sometimes it works, and sometimes it doesn't. Would you please give me any suggestion on the DCM reset signal?

I noticed there is a proc_sys_reset core in the EDK kit, is that a good idea to use this core and generated reset signal? The proc_sys_reset has a DCM_locked input and says it should be connected to the DCM which achieved the lock last when there are several DCMs in the system. But my DCMs are not chained and I don't know which one will achieve lock last. Is there a way to and all the lock signals of DCMs in the EDK and tie it to the proc_sys_reset core?

Thanks a lot, Rebecca

Reply to
Rebecca
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You can and all of the signals together using the util_reduced_logic core in EDK. Look in the IP Catalog under Utility.

Did you start your design with the Base System Builder? If so, it should have put a reset core in the design for you. If not, add one in.

Regards,

John McCaskill

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Reply to
John McCaskill

Rebecca,

If you are using Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5:

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For Spartan parts:

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There are a number of small details that might cause the DCM to not lock, or lose lock:

1) clock feedback does not arrive in time after reset 2) clock frequency is changing as the DCM is trying to lock 3) clock has too much jitter 4) clock has missing pulses (bad signal integrity, noise, etc.)

Depending on which part you are using, you need to review the above literature, as well as read the chapter in the respective user's guide.

Austin

Reply to
Austin Lesea

Thank you very much for your reply. I will read the document and have a try.

Reply to
Rebecca

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