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Rocket IO clocking

I have a problem with the RocketIO component. The documentation says that I need a differential clock for the Rocket IO. I am using Xilinx EDK 8.2. The input frequency is 100 MHz. The bus frequency is 50 MHz. So a DCM has been included by the EDK. When I want to use the Rocket IO I have to generate a differenatial clock. The problem is, that I need an IBUFGDS to do that. But an IBUFGDS has to be connected to a pad. Otherwise NGDBUILD will produce an error telling me that signal XYZ is has multiple drivers and is driving non-buffer primitives. . There is no such thing like a BUFGDS. But since the input for the IBUFGDS is the 50 MHz clock from the DCM the IBUFGDS can not be connected to a pad. If I do not use the IBUFGDS I get a synthesis error. So what am I supposed to do in this situation?

Thanks in advance Sebastian Goller

Reply to
Sebastian Goller
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Sebastian,

I believe the documentation recommends using a differential clock on the board to supply one of the BREF inputs (which certian of the dedicated clock inputs) if the data rate is to be high e.g. above 2.5 GBps. This would require a differential input buffer, it is also recommended to connect this clock directly to the BREF clock input on the MGT and not use DCM's as they introduce to much jitter. For the user clock I think you are ok using internal clocks which have been generated by a DCM. If you are using data rates lower than 2 Gbps you can use the REFCLK inputs of the MGT these do not have to brough in via a differential input though it is still not recommened to use a DCM to generate REFCLKS due to the jitter introduced. see UG024.pdf from xilinx.

generated externally to the FPGA by either a oscilator in which case a differential input is recommended or a frequency synthesiser (we do this and it works ok) alternatively you could just use the 50 MHz clk

Hope this makes sense, I wrote it rather quickly

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Reply to
adam.taylor

I believe the documentation recommends using a differential clock on the board to supply one of the BREF inputs (which are specific ones of the dedicated clock inputs) if the data rate is to be high e.g. above 2.5 Gbps. This would require a differential input buffer, it is also recommended to connect this clock directly to the BREF clock input on the MGT and not use DCM's as they introduce to much jitter.

To drive REFCLK's as opposed to BREFCLKS I think you can use any clock internal to the FPGA as long as it is driven from a BUFG. Though for REFCLKS it is not recommended to use DCM generated clocks due to jitter on the outputs.

You can use the REFCLK inputs to the MGT provided the speed is below

2.5 Gbps UG 024 provides more info

For the user clock you are ok using internal clocks which have been generated by a DCM.

You do not say if the 100Mhz clock you have divdied down to 50 MHz is for a reference clock (BREF or REF clk) or for the user clock ? You should be ok if the DCM is driving the user clock but may have problems if it is going to be driving the reference clocks.

Hope this makes sense, I wrote it rather quickly

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Reply to
adam.taylor

There is a strict jitter specification for the RocketIO input clock.

The DCM output will completely violate this tightly spec'ed value.

In over-simplified terms, the clock multiplication needs to know where the clock is within an *output* bit period; if the jitter is a large part of a bit period (or more than a bit) how could the the timing be effectively implemented?

Reply to
John_H

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