I have a simple design (about 300 logic elements / 150 registers) written in Verilog. It's highly self-contained (only about ten signals on the interface).
(For the curious, it performs a function for analogue video).
It's now proposed to incorporate this in a design which is otherwise VHDL (and over which I shall have no control).
Obviously, the Verilog could be converted, but this would be significant work (and I no have no experience at present of VHDL). For this reason (and particularly since the interface is simple), I'd like to keep my part of the design in Verilog.
Is mixed-language design well-supported? If so, does anyone have general advice or words of caution?
You did not tell us what tools you are using, here or in that other thread!
We use a mixture of VHDL and Verilog with almost no problems. Our tool set of interest is EDK/ISE and ModelSim. We have both cases of VHDL instantiating Verilog, and Verilog instantiating VHDL.
The one problem that we have come across is in passing 32 bit generics from VHDL to Verilog when the MSB is set. In this case it is when passing bus address assignments. I don't remember the exact details other than it being related to signed vs unsigned, but ISE required us to perform one conversion on the generics before passing them, and ModelSim required something else.
There are more than a few quirks in ISE with regard to mixed language design. ModelSim XE won't support it - you need to buy at least the PE version. I've had some issues with synthesis in XST where strange errors cropped up if the VHDL code and the Verilog code both instantiated the same Xilinx primitives. Most of the synthesis problems go away if you package up all of your Verilog into an NGC file and use it as a black box in VHDL (or vice versa). Still I think it's important to have the mixed language simulation tools. Just a matter of money...
You'll need a simulator with a license for mixed language, which will generally cost considerably more than a single language license. If your synthesis tool does not support mixed language, you can black box the other language sub-design in the larger design, synthesize them separately and put the edifs in the same directory. The xilinx tools will stitch the edifs together without any problems.
Yes, ModelSim is the most expensive tool we have. We use both the PowerPCs and the MGTs, so XE was not an option for us. EDK will allow you to simulate a mixed language design with a single language simulator by synthesizing the parts of the design in the language you do not have a license for and generating a post synthesis netlist in the language you do have a license for. That might work for a small part of the design which is already known good. We tried to use that method very briefly before deciding that it was not worth it and upgrading our license. We ended up using ModelSim PE plus with the extra licenses for mixed language, swift models, and code coverage.
Other than the difference between how ModelSim and ISE required us to pass parameters, we have not seen any problems with mixing languages. EDK does synthesize each core in the design separately, then combine the netlist in a second pass so maybe that has simplified the situation enough to avoid the problems that Gabor has seen. Even taking how EDK partitions the synthesis, we still have all cases of VHDL using Verilog, and Verilog using VHDL, and having both of them as leaf nodes in the hierarchy of a given core.
I have also seen mention of programs to convert Verilog to VHDL and VHDL to Verilog, any one here try them and have any comments on the results?
I once did this with Quartus. I thought the free version did it, but I had a licensed version so I can't be sure.
I did mixed AHDL, VHDL, verilog, and schematic capture all in one.
With the schematic based parts the ports don't have an order so they all have to be specified by name. Many port names started with a digit, which verilog can do, but it is a little more work.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.