Hi all, My problem is more of a VHDL problem but... I need to create the following pyramid alike design.
in my declarative part i need to declare the following signals :
signal reg1 : std_logic ; signal reg2 :std_logic_vector (1 downto 0); signal reg3 :std_logic_vector (2 downto 0); .. .. signal regN :std_logic_vector (N-2 downto 0);
afterwards I need to connect them as follows :
if rising_edge (clk) then
reg1
"Moti" schrieb im Newsbeitrag news: snipped-for-privacy@z14g2000cwz.googlegroups.com...
Use a 2D array like this.
type my_array is array(N downto 0) of std_logic_vector(N downto 0);
signal my_pyramid is: my_array;
Regards Falk
Moti a écrit :
[...]Hi As far as I can see, you can't declare n signals in a concise & elegant way unless you declare an array (which will be twice bigger than what you need but should be optimized by the synthesis tool) I don't think "generate" is what you need. I would write: ... in_signal : in std_logic_vector(n-1 downto 0); out_signal : out std_logic_vector(n-1 downto 0); ... type bidim_array is array (n-1 downto 0, n-1 downto 0) of std_logic; signal reg : bidim_array; ... process (rst, clk) if rst = '1' then reg (others => others => '0'); -- not sure of the syntax here elsif rising_edge(clk) then for i in 0 to n-1 loop reg(i, 0) 0 then for j in 1 to i loop reg(i, j)
Thanks Falk and Nicolas,
the NxN array seems like a good idea - I was just looking for some more elegant solution (like a special generate) for the code to be more readable.. But it looks like I have no choise.
Nicolas, special thanks for the code example it is a very nice implementation. and BTW the right array reset syntax is -> reg (others => '0' ) ) ;-)
Thanks, Moti.
Moti a écrit :
Thanks :o) I thought that was for arrays of vectors only, not 2D arrays...
-- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/
more
You always have a choice. For recursive hardware structures, choose confluence:
- component pyramid +count +in -out is
- if width in == 0
- out = ''
- else
- out = {pyramid (count + 1) ('msbs' in) $} '++'
- {regs 1 count ('lsb' in) $}
- end
- end
-Tom
Why not use Confluence to generate your low level components, then instantiate them into your higher-level designs?
(Note: Confluence 0.9.3 is the latest version with support for VHDL.
0.10.0 is Verilog-only at this point. VHDL will be back on-board with 0.10.1.)-Tom
A possibility is to do it with a recursive call to a component, one call for each level of the pyramid. Your code needs an end condition in it to terminate the recersive calls. A long while back, I did some adder trees this way, and it broke some of the tools (notably Synplify). I am pretty sure the bug that caused it to break is now fixed, although I have not checked it in some time.
In otherwords, you use a generate on one level to generate the logic for that level and an instantiaton of that same component to generate the next level. The terminating condition instantiates a different terminating component or just avoids the call. I'd have to dig out some of my old code that does this.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Quartus is still broken for recursive component instantiation AFAIK, and I am pretty sure that some other tools have similar problems.
Recursive instantiation badly confuses the automatic hierarchy traversal machinery in Xilinx ISE, so that you have to choose the top-level design by hand, but I seem to remember that the synthesis tool itself is OK with it.
-- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Ray, I managed to do the recursive call but my problem was in the declaration part I didnt knew how to the declare the signals as I mentioned in the begining of the thread.
eventually I took Nicolas Matringe advise and declared a complete bidim array (width-1,width-1) - that is actually twice the size I needed and the synthesizer optimized half of array for me. the code relevant section is attached.. and it's working too ;-)
BTW - I did it in order to create a delay network for an 32 bit NCO design at 300MHz.
Regards, Moti.
signal c : std_logic_vector (width-2 downto 0); signal accumulator_reg : std_logic_vector (width-1 downto 0); signal b_delayed : std_logic_vector (width-1 downto 1);
type bidim_array is array (width-1 downto 1, width-1 downto 0) of std_logic; signal reg : bidim_array;
begin
process (clk,resetn) begin if resetn = '0' then reg (others => '0')); if rising_edge(clk) then--elsif rising_edge(clk) then for n in 1 to width-1 loop reg (n,0)
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.