Altera synthesis of registered signals ???

Dear Sir or Madame,

I have the following problem:

In a clocked process I made the following registered signal assignments:

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------------------------------------------------------------ entity xy is port( addr_to_send : in std_logic_vector(6 downto 0); ep_to_send : in std_logic_vector(3 downto 0); addr_rec : in std_logic_vector(6 downto 0); ep_rec : in std_logic_vector(3 downto 0); direction_to_send : in std_logic; cam_ram_entry_valid : in std_logic; ... ); end xy;

architecture ...

process(write_clock) begin if rising_edge(write_clock) then

l_data_addr_to_send