Creating a vector out of other vectors


I have the following problem:

library ieee; use ieee.std_logic_1164.all;

entity test is port(ep_to_send : in std_logic_vector(3 downto 0); addr_to_send : in std_logic_vector(6 downto 0); data_valid_to_send : in std_logic; direction_to_send : in std_logic ); end test;

architecture rtl of test is signal test_vector: std_logic_vector(9 downto 0);

begin test_vector

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Yep, perfectly legal code. Just be sure that the size on the left and right are equal. And you don't need the parenthesisses. I just prefer to use those things as less as possible. Your code will do the following: test_vector(9)

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Jan De Ceuster

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