Creating a vector out of other vectors

Hi,

I have the following problem:

library ieee; use ieee.std_logic_1164.all;

entity test is port(ep_to_send : in std_logic_vector(3 downto 0); addr_to_send : in std_logic_vector(6 downto 0); data_valid_to_send : in std_logic; direction_to_send : in std_logic ); end test;

architecture rtl of test is signal test_vector: std_logic_vector(9 downto 0);

begin test_vector