Ive seen posts on this error in VHDL a few times around here, but I am still unsure how to get rid of this error so my nets don't get removed. Here is the code that is causing the error:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity BLINK is
PORT( SA: IN STD_LOGIC_VECTOR (19 downto 0); --Offending input vector pin2: OUT STD_LOGIC := '0'; clk: IN STD_LOGIC);
end BLINK;
architecture FLASH of BLINK is
CONSTANT count: INTEGER:=8330000; SIGNAL t: INTEGER:= 0; SIGNAL sig: STD_LOGIC:='0'; SIGNAL state: STD_LOGIC; CONSTANT address: STD_LOGIC_VECTOR (19 downto 0) := X"002E8"; SIGNAL BASEADDRESS: STD_LOGIC_VECTOR (19 downto 0); SIGNAL ADD: STD_LOGIC_VECTOR (2 downto 0);
begin
PROCESS (clk, SA) --SA is placed in sensitivity list begin
BASEADDRESS