Hi,
I have a problem with Forward-Annotating multicycle, false path constraints from Synplify Pro 7.7.1 to Quartus 4.2 . I have given all the multicycle and false path constraints to Synplify Pro. It is being taken by Synplify and writing to design.tcl file also. The same design.tcl file i am using for porting constraints to Quartus. Whatis happening is in the netlist output given by Synplify, some of the multicycle/false path destination registers have become combo logic(i really don't know why?), and being ignored by Quartus. In fact, there are some valid multicycle registers, terminated by (or through) that combo logic. But the destination register, is not forward annotated by Synplify. Since Quartus sees only a combo logic, and not able to find the destination register(which is the actual multicyle path), its ignoring my assignments. This gives me a lot of timing violations also. There are more than 100s of such multicycle registers, so manually searching and changing to correct registers, is not an easy task, and bound to mistakes. Have anybody encountered these types of problems? Please help me solve this issue.
Thank you,