Memory initialization for synthesis in ISE

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I am using the Core Generator to create memories. I used the COE file to
initialize them and I simulate behaviour.
When I tried to Post-Place & Route, it seems that the memory does not get
initialized with the same values as on the behaviour simulation. Any idea
was is not going OK?

In other words, is there a way (in Xilinx ISE) to initialize CoreGen created
memories for synthesis (NOT simulation). And if yes, how exactly?


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