Coregen difficulties with DCT

Oct 10, 2004 2 Replies
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Has anyone used the DCT core available in Xilinx ISE 6.1's coregen? I am currently getting the following error message in the translate stage:



ERROR:NgdBuild:604 - logical block 'u2' with type 'DA_2D_DCT' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'DA_2D_DCT' is not supported in target 'spartan2'.



I get a similar error message reguardless of the device I select. I instantiate as directed in the .vho file. Does anyone know what I am doing wrong?



Brandon Sterner


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J

Brandon, You're probably doing nothing wrong. There is an old bug in the ISE S/W, dating back to 1-D DCT apparently. Check through the answer database on the Xilinx site, and find Record Number: 17816, which will tell you "To resolve this issue, disable the "Read Cores" option within the synthesis properties. For XST, select Synthesis options ->

Read Cores to disable this option." HTH, John

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Thanks this helped a lot. At first I had trouble finding the "read cores" option. It turns out I had to select advanced mode by going to edit->preferences->processes and change property display level from standard to advanced. Thanks again, this saved me from having to write my own.

Brandon

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