Constraint on a asynchronous signal

Feb 02, 2005 1 Replies
C

hi,



I'm working in VHDL with ISE6.3 and ModelSim5.3. I'm using synchronous and asynchronous reset.



process(clk,ARST) if ARST='1' then



-- elsif rising_edge(clk) then if SRST = '1' then -- else -- end if; end if; end process;



I put constraint on synchronous reset, but I don't know constraints need by an asynchronous reset. When I simulate my design, it's working with the synchronou reset and I have Hold/setup error with asynchronous reset.


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B

Hi,

Probably you can try the following

1.constrain asynch reset to pass through a global net- this will clean the hold violations.

2.To clean set-up violations- may be you have to take care adjust time between asynch reset removal and clock active edges. Hope this will help.

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