Define the primary clock with XST in VHDL

Use a simulator to verify correct functional operation of your top level design...after that you should find that XST synthesizes your design properly.

KJ

XST or quartus synthesis will find the clock in vhdl code that matches a synchronous process template. There are many ways to do this. Here's one:

architecture synth of sync_template is begin sync_template : process(reset, clock) is -- begin -- process template if reset = '1' then init_regs; -- init code here elsif rising_edge(clock) then update_regs; -- update code here end if; update_ports; -- port assignments here end process sync_template; end architecture synth;

details here:

-- Mike Treseler