inefficient mux synthesis in quartus

Hi Eliben,

The constructs are NOT the same. In the loop example you infer a latch situation in case byte_cnt is not between 0 and 24, which Quartus will cater for. In the unrolled version you made I am 99.9999% sure that it ends with

elsif byte_cnt = 23 then data_reg

I don't know about the efficiency, but why do you need a loop to describe this mux? Can't you just use byte_cnt directly in your assignment to data_reg?

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I'll give it a try. Thanks !

Eli

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I'm not sure about synthesis, but Modelsim doesn't eat it - it wants a constant expression in the array indices. I tried it before I created the "for" hack, it didn't compile.

Eli

Another reason the for loop isn't equal to if..elseif: The for loop checks the variable against the loop value for every iteration of the loop reguardless fo past equality, like a series of ifs without any elseifs. You need to break out of the loop inside the if statement to make it similar to if..elseif.

At least, I think I read something like that on here before. I don't know enough about it yet to be sure that I'm remebering correctly.

-Extrarius

Hi eli,

Just a few statistics:

Using Quartus II 4.1 SP2, the following code

==== Cut here ==== library ieee; use ieee.std_logic_1164.all;

entity zort is port ( clk : in std_logic; inbus : in std_logic_vector(199 downto 0); sel : in integer range 0 to 24; outreg : out std_logic_vector(7 downto 0) ); end zort;

architecture rtl of zort is begin process(clk) begin if rising_edge(clk) then outreg

You might try writing to Ben Cohen about this since it is in his book. The title is "HDL Chip Design", the example is in section 7.9 Multiplexer Model, p 202-203. Here is the code example...

library IEEE; use IEEE.Std_Logic_1164.all; use IEEE.Std_Logic_Arith.all;

entity Mux is port (DataIn : in Std_Logic_Vector(17 downto 0); MuxSelect : in Std_Logic_Vector( 4 downto 0); MuxOut : out Std_Logic); end Mux;

architecture Mux_a of Mux is begin -- Multiplexer 18 to 1 MuxOut