Sensitivity list

here:

The sensitivity list indicates to a simulator which signals to watch for changes. In this case if you wanted to synthesize an asynchronous latch for preset, normally any time reset is active changes on preset would trickle through to count. Thus the simulator would want to watch for changes in preset during this time and would need preset in the sensitivity list to do that.

As coded, a simulator would only look at preset on change of reset or clk. This would correspond to a multi-edge-triggered flip-flop that the FPGA cannot create. That's why the synthesizer complains. Since you got a warning and not an error, my guess is that the synthesizer made the latched preset you intended, however your synthesized result will not match you behavioral simulation.

Hope this helps, Gabor

You receive this WARNING because you use a signal declaration for the preset. In this case, you have to add 'preset' in the sensitivity list.

But it is not a good implementation to using dynamic signal for initializing registers (your count) via a asynchronous reset.

a) I would put your preset in a generic declaration. b) Or I would use a synchronous reset schem for your preset

Best regards, Laurent www.am> Hi,

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-- See

It represents a list of signal events to wait for at the end of the process.

It shouldn't. Ignore or disarm the warning.

-- Mike Treseler

Thanks for your answers!

Yes it should. Take a close look at the code.

The warning can be safely ignored for synthesis (at least with all synthesis tools I have seen). And assuming preset never changes, it can be safely ignored for simulation. But if preset does change, the simulation will not match the hardware.

The correct fix is to write the code correctly, not ignore the the warnings. Laurent has the correct fix.

Sorry. You are correct. It should be a synchronous load.

-- Mike Treseler