VHDL warning " Feedback mux " from synplify pro ...thx

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You don't really want the process sensitive to events on MaxSearchEn, I assume that signal is meant to be a clock enable.

Regards, Allan.

Also, your clock enabled processes should look something like:

label : process(clk, reset) begin if reset = '1' then ... elsif rising_edge(clk) then if clk_enable = '1' then ... end if; end if; end process;

Comments:

1. You don't need () around the condition in an IF statement. You're not writing C (or Verilog)!

1. rising_edge(clk) is a lot clearer than clk'event and clk='1'. There are some minor semantic differences that probably won't worry you.

2. Use separate IF statements for the rising_edge and clk_enable parts. It's easier to read, and some synthesisers may have problems if they're combined into the one condition.

1. VHDL doesn't force you to label processes, but I find it makes it easier to read the code if they are labeled, assuming you choose labels sensibly.

Regards, Allan.

That structure makes an implied memory element for bitsync_temp in the case pnt