Hi, Why is it that you cant put a FDRE and an SRL16E on the same slice? I looked at a V2 slice within FPGA Editor (woohoo, got the full version of ISE at last!) and it shows me there's a WE signal going to the SRL16, driven by the slice's SR input. Now why would you want to drive it with the SR input when there's already a CE input available??? I wanted to construct a delay line (SRL16 + FF), whose output FF can be reset but then this is not allowed. Any workarounds? Thanks. -Jim
- posted
19 years ago