what is a better approach to synthezise synchronous reset on FPGA?

Hi Valentin,

The first one is the better way to do it. The second will only work if your enable is high.

Let me open another can of worms by saying 'why do you want a reset at all?'. Resets in *most* cases simply use up logic and routing resources unnecessarily as all the fpga elements are initialised on powerup. You can even control the initialisation states of individual registers if necessary. In *most* cases resets are mainly there to make simulations look good by removing unknown signal conditions.

You may even miss out on some very useful resources if you automatically apply resets to all your code... for example if you are using a Xilinx Virtex device and you infer a shift register (i.e. 16 bits) in your HDL, you will not be using a single SRL (Shift Register LUT) element, you will be using 16 registers.

Food for thought ;)

Regards,

Well, quite clearly, the second will reset only if the ENABLE signal is asserted. Is that your desired functionality?

-a

I guess it depends on what you are trying to do. The first one describes a familiar D Flip Flop with synchronous reset and clock enable. This is the same as FDRE in Xilinx library. In the first case, the clock enable signal is only required for one case. It is required if a user wants to transfer data from the input to the output (D to Q). Clock enable signal is irrelevant when you want to reset the flip flop. The 2nd case also describes a similar flip flop. But in this case, the clock enable is required for both cases. It is required if a user want to reset the flip flop and if a user wants to transfer data from D to Q.

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And when you target an ASIC? Is it ok to have registers without a reset in an ASIC? What about the scan chain for BIST?

Martin

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In the title of this thread - he did specifically ask about 'Synchronous reset on FPGA'

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On the "can of worms"...since it is allready opened: If you don't have a reset how you bring the FPGA logic into a known state without power cycle?

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But my question is still open ;-)

Do I need a reset for every flip-flop in an ASIC? I want only use designs in an FPGA which are not to hard to transfer to an ASIC. With some care only the memory models have to be exchanged and as I know there are tools to add the BIST circuits 'on top' of the design. Have been involved in an FPGA design that was transfered to an ASIC, but all flip-flops where reset (there was discussion about asynch. vs. synch reset).

Martin

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---------------------------------------------- JOP - a Java Processor core for FPGAs:

"Steve Merritt" schrieb im Newsbeitrag news:ehvfc.339$ snipped-for-privacy@newsfe2-gui.server.ntli.net...

'Synchronous

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You get a known state after configuration (you don't need a power up).

All flip-flops are in a defined state after configuration. But if 0 or 1 is the default state depends on your logic and synthesis tool. In Quartus you'll get a warning when some filp-flops power up 1 (power up is configuration). In reality all registers are cleared, but optimization can change the logic in a way that some registers are inverted and will be effectively 1 with respect to your original logic.

You can use this default state to generat an internal reset for some logic without an external reset pin. E.g.:

--

-- intern reset

-- signal int_res : std_logic; signal res_cnt : unsigned(2 downto 0);

begin

process(clk_int) begin if rising_edge(clk_int) then if (res_cnt/="111") then res_cnt If you don't have a reset how you bring the FPGA logic into a known

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