Your examples show exactly the difference between sync & async resets. Your 1st process will reset on the input, regardless of what the clock is doing. The synthesiser will use an asynchronous reset, if it's available. If it isn't, synthesis will (should?) fail.
Similarly, the 2nd process is synchronous, with clock governing reset. The synthesiser will use a synchronous reset, if it has one. If not, it will usually create one, by adding an AND gate right at the flipflop's input.
If you have g :Hi @ all, : :it is one possibility to :synchronize an asynchronous reset so that all flip flops in :the FPGA are resetted within the same clock period. : :Using this synchronized reset :can I still write the process like that: : : :process(Sync_reset, Clk) :begin : if Sync_reset='1' then : ... : elsif rising_edge(Clk) then : ... : end if; : :end process; : :or does it make more sense to write it like that: : :process(Sync_reset, CLk) :begin : if rising_edge(Clk) then : if Sync_reset='1' then : ... : else : ... : end if; : end if; :end process; : :I would be very thankful for your opinion. : :Rgds :André