When creating custom IP Cores for inclusion in to EDK projects, I stumbled across the following problem:
If a custom core (in VHDL) does not have a generic section as for example:
----------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all;
entity my_inverter is port ( I : in STD_LOGIC; O : out STD_LOGIC ); end my_inverter;
architecture arch_my_inverter of my_inverter is
begin O I, O => O );
end architecture STRUCTURE;
-----------------------------------------------------------
And than complains when compiling the code it just generated:
Compiling vhdl file /home/rudi/projects/system/synthesis/hdl/rst_inverter_wrapper.vhd in Library work. ERROR:HDLParsers:164 - /home/rudi/projects/system/synthesis/hdl/rst_inverter_wrapper.vhd Line 25. parse error, unexpected CLOSEPAR, expecting IDENTIFIER