Hi. I have a xc2v8000 design (70% utilization).
With the same EDIF netlist the Xilinx routability changes dramatically with frequency:
Clock constraint: 25 MHz -> routed design Clock constraint: 50 MHz -> 1200 un-routed wires Clock constraint: 100 MHz -> 60000 un-routed wires
Unfortunately 100 MHz is my target frequency...
Is there a flag that tells the Xilinx P&R to prefer routing over timing at the first phase, and do speed optimization only afterwards?
ThankX, John
First run a timing analysis after mapping, before P&R, at 100 MHz (or even faster). This tells you the maximum speed you can expect with infinitely good routing. If there are any paths failing to meet timing, you need to modify the design to remove the timing bottleneck (reduce logic levels between registers), and generate a new EDIF file.
Improving the EDIF file will also work to improve the speed of placed/routed designs, but you also have other options, such as floorplanning, to improve the placement (which simplifies the routing problem by ensuring related logic is placed together)
- Brian
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