Hi. I have a xc2v8000 design (70% utilization).
With the same EDIF netlist the Xilinx routability changes dramatically with frequency:
Clock constraint: 25 MHz -> routed design Clock constraint: 50 MHz -> 1200 un-routed wires Clock constraint: 100 MHz -> 60000 un-routed wires
Unfortunately 100 MHz is my target frequency...
Is there a flag that tells the Xilinx P&R to prefer routing over timing at the first phase, and do speed optimization only afterwards?
ThankX, John